1. Field of the Invention
The present invention relates to logic circuits, and more particularly to logic gates with improved operating speed and noise properties.
2. Discussion of Related Art
NAND and NOR gates are the basic logic elements used for representing a digital logic circuit in a semiconductor integrated circuit. In general, the logic elements used in a digital logic circuit include AND, OR, NOT, NAND, NOR, XOR and XNOR gates. All these logic elements do not have a different circuit from each other. Instead, a combination of NAND, NOR and NOT gates defines circuits of the other logic elements. For instance, the circuit of an AND gate is defined by connecting, in series, a NOT gate to the output of a NAND gate. The circuit of an OR gate is defined by connecting, in series, a NOT gate to the output of a NOR gate.
FIGS. 1A, 1B and 1C are the logical symbol, truth table, and circuit, respectively, of a related art NAND gate. In FIG. 1A, A1 and B1 are input signals, and Z1 is an output signal. A logical value of output signal Z1 is determined by the logical values of the, two input signals A1 and B1. FIG. 1B is the truth table of output signal Z1 based on input signals A1 and B1. When at least one of A1 and B1 is 0 (VSS), output signal Z1 becomes 1 (VDD). On the other hand, when both input signals A1 and B1 are 1, output signal Z1 becomes 0.
In FIG. 1C, two PMOS transistors MP11 and MP12, of which sources are supplied a power supply voltage VDD, are connected in parallel to form a pull-up circuit. The gate of PMOS transistor MP11 is supplied the first input signal A1 and the gate of the other PMOS transistor MP12 is supplied the second input signal B1. The drains of the two transistors MP11 and MP12 are connected to each other to form a common node.
Two NMOS transistors MN11 and MN12 are connected in series between the common node and ground VSS to form a pull-down circuit. The gate of NMOS transistor MN11, which is directly connected to the common node, is supplied input signal A1 and the gate of NMOS transistor MN12, which is connected to the ground VSS, is supplied input signal B1.
When at least one of the two input signals A1 and B1 is 0 (VSS), at least one of the two PMOS transistors MP11 and MP12 is turned on, and at least one of the two NMOS transistors MN11 and MN12 is turned off. Therefore, output signal Z1 becomes 1 (VDD). On the other hand, when both input signals A1 and B1 are 1, the two PMOS transistors MP11 and MP12 are turned off, and the two NMOS transistors MN11 and MN12 are turned on. Therefore, output signal Z1 becomes 0.
FIGS. 2A, 2B and 2C are the logical symbol, truth table, and circuit, respectively, of a related art NOR gate. In FIG. 2A, A2 and B2 are input signals and Z2 is an output signal. A logical value of output signal Z2 is determined by the logical values of the two input signals A2 and B2. FIG. 2B is a truth table of output signal Z2 based on input signals A2 and B2. As shown in the truth table, when at least one of the two input signals A2 and B2 is 1, output signal Z2 becomes 0. On the other hand, if both of the two input signals A2 and B2 are 0, output signal Z2 is 1.
In FIG. 2C, two PMOS transistors MP21 and MP22, of which sources are supplied the power supply voltage VDD, are connected in parallel to form a pull-up circuit. The gate of PMOS transistor MP21 is supplied the input signal A2 and the gate of PMOS transistor MP22 is supplied the input signal B2. Two NMOS transistors MN21 and MN22 are connected in parallel between the drain of PMOS transistor MP22 and the ground VSS to form a pull-down circuit. The gate of NMOS transistor MN21 is supplied input signal A2 and the gate of NMOS transistor MN22 is supplied input signal B2.
When at least one of the two input signals A2 and B2 is 1, at least one of the two PMOS transistors MP21 and MP22 is turned off, and at least one of the two NMOS transistors MN21 and MN22 is turned on. Therefore, output signal Z2 becomes 0. On the other hand, when both input signals A2 and B2 are 0, the two PMOS transistors MP21 and MP22 are turned on and the two NMOS transistors MN21 and MN22 are turned off. Therefore, output signal Z2 becomes 1.
As described above, in a NAND gate or a NOR gate of the related art, the output signal fully swings between the levels of the power supply voltage VDD and the ground voltage VSS. Therefore, high-speed operation and low power consumption can not be expected. Also, since the highest levels of the input/output signals are in a single mode, a power supply voltage and ground voltage, if the power supply voltage is varied because of temperature variations, the output signal fails to have a stable logic value. As a result, the reliability of circuit operation is remarkably reduced.